Silicon on insulator (SOI) substrates usually include a bulk substrate (also referred to as handle wafer substrate), a buried oxide dielectric (also referred to as insulating layer, BOX) and an active layer (also referred to as top silicon). SOI wafers need to be specified in a way such that unwanted non-equilibrium conditions are prevented at the interface between the bulk substrate and the buried oxide dielectric. These unwanted non-equilibrium conditions can be triggered by sudden bias changes of structures in the top silicon. A non-equilibrium condition can be a deep depletion state and an incomplete inversion. The deep depletion state can be recovered by thermal generation of minority carriers. However, this can take seconds to several minutes, during which the displacement currents of the recovering regions disturb high precision, low current leakage electrical circuits (for example high impedance JFET input stages or switched capacitor circuits). Deep depletion states can occur if the doping polarity of the handle wafer is of the same type as the bias potential of the top silicon (positive voltage surge over p-type handle wafer or negative voltage surge over n-type handle wafer). In order to prevent non-equilibrium states, an appropriate polarity of the handle wafer material may be chosen or the doping concentration of the handle wafer may be increased. However, there are cases in which the polarity of the handle wafer cannot be chosen arbitrarily as the bias voltage level may be negative and/or positive with respect to the handle wafer. In this case, the handle wafer doping needs to be increased sufficiently in order to prevent inversion and the associated deep depletion effect. Although increasing the doping of the handle wafer may be possible for low voltage technologies, an increased handle wafer doping may conflict with the requirement of low doping concentrations of active high voltage components (bipolar collectors, JFET gates) for high voltage technologies. For high voltage technologies the increased doping concentration of the handle wafer can cause auto-doping of the lower doped active silicon regions which can adversely affect the functionality of the circuit.